1. Field of Invention
The present invention relates to a burn-in method for synchronous memory. More particularly, the present invention relates to a method for generating burn-in signals to simulate the normal operation of synchronous memory including burst mode and pipeline functions.
2. Description of Related Art
In general, asynchronous burn-in method for asynchronous memory is used for carrying out the burn-in of conventional synchronous memory. For example, conventional extended data output (EDO) DRAMs are burn-in by the asynchronous method. However, for synchronous memory, if an asynchronous method is used in the burn-in operation, a number of advantages offered by a synchronous method are left out, and hence the possibility of hiding some untested situations are real. For example, the speed of operation tested by an asynchronous method is only half of the actual speed of operation for a synchronous memory, which can entail a high risk to the product. Furthermore, the synchronous memory tested by an asynchronous burn-in may not meet the demands in an actual working environment.
FIG. 1 is a diagram showing the pin layout of a conventional synchronous memory package. FIG. 1 shows an example of a DRAM produced by NEC with the product label .mu.PD4516821. FIG. 2 is a timing diagram for carrying out an asynchronous burn-in operation for a synchronous memory as shown in FIG. 1.
As shown in FIG. 2, a clock pulse signal CLK in cycle T201 pre-charges the DRAM in group A, and then another clock pulse in cycle T202 pre-charges the DRAM in group B. Next, about eight clock pulses are used in cycle T203 for auto-refreshing the whole group of memory, and then the burn-in method is selected in clock pulse cycle T204. Conventionally, an asynchronous testing method is selected here. Thereafter, a clock pulse cycle T205 with no operation is effected purely as a time delay. Then, the exercising of data storage and retrieval for the DRAM begins.
As shown in FIG. 2, because an asynchronous burn-in method is selected, the subsequent clock pulse CLK for the storage and retrieval of data Dasy must go through the sequence of first activating the DRAM in group A in cycle T206, performing a write operation for the DRAM in group A in cycle T207, pre-charging the DRAM in group A in cycle T208, activating the DRAM in group B in cycle T209, performing a write operation for the DRAM in group B in cycle T210, pre-charging the DRAM in group B in cycle T211 and so on (because pipelining architecture divides the DRAM into a group A and a group B). Consequently, only 4 groups of data Dasy are written into the DRAM in the 12 clock pulse cycles CLK from T206 to T217, and hence the burst output mode and pipelining function of a synchronous memory are not exercised.
In light of the foregoing, there is a need for improving the burn-in method for exercising the underutilized functions as well.